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GP4020
GPS Receiver Baseband Processor
DS5134
ISSUE 4.4
May 2002
Features
* Complete GPS correlator and Firefly MF1 microcontroller core * ARM 7TDMITM (Thumb(R)) Microprocessor, with JTAG ICEBreakerTM Debug Interface * Fully Configurable External Data Bus * 12 Fully Independent Correlation Channels * Low Voltage Operation: 3*3V * Low Current Power-Down Mode * 1PPS UTC Aligned Timing Output * Dual UART * 3-wire BILD Serial Input/Output (BSIO) Interface * 8 General Purpose Input/Output (GPIO) Lines * Boot ROM, allowing Software Upload via UART * 8K Bytes Internal SRAM * Compatible with GP2015 and GP2010 RF Front Ends
Ordering Information
GP4020/IG/GQ1N (trays) GP4020/IG/GQ1Q (tape and reel, 1000 units per reel) The GP4020 is available in a 100 pin PQFP package in Industrial (-40C to +85C) grade. The ordering code is standard for screened devices
Description
The GP4020 is a complete digital baseband processor for a Global Positioning System (GPS) receiver. It combines the 12-channel correlator function of the GP2021 with an advanced ARM7TDMI (Thumb) microprocessor to achieve a higher level of integration, reduced system cost, reduced power consumption and added functionality. The GP4020 complements the GP2015 and GP2010 C/A code RF downconverters available from Zarlink Semiconductor. The correlator section contains 12 identical tracking module blocks, one for each channel. Each channel contains all the components necessary for acquiring and tracking the received signal, and also contains other functional blocks, which are used to produce part of the measurement data set. Individual channels may be deactivated for systems not requiring full 12-channel operation and thus allowing for reduced power consumption and processor loading. The microprocessor section contains the Firefly MF1 microcontroller core, which includes an ARM7TDMI with a Thumb instruction de-compressor plus the Firefly BILD module. Also included are a second UART, BILD Serial I/O, General I/O and Watchdog functions.
Applications
* * * * *
GPS Navigation Systems GPS Geodetic Receivers Time Transfer Receivers Automatic Vehicle Location (AVL) E911 Emergency Positioning
Related Products
Part GP2015 GP2010 Description GPS Receiver RF Front End (TQFP 48 package) GPS Receiver RF Front End (PQFP 44 package) Data sheet DS4374 DS4056
Absolute Maximum Ratings
Supply voltage (VDD) from ground (GND) -0*5V to +5*0V Bias for 5V inputs +7*0V max. Input voltage (any input pin) GND-0*5V to VDD+0*5V Output voltage (any output pin) GND-0*5V to VDD+0*5V Storage temperature -55C to +150C Static discharge (HBM)* 2kV *Mil Std 883 Human Body Model = discharge from 100pF through 1500 between any 2 pins
Manufactured under licence from ARM Ltd ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd
GP4020
POWER_GOOD NRESET DISCIO MULTI_FNIO RTC_XOUT
GPIO[7:0]
GPIO[7:0]
WDOG
GPIO BSIO
GPIO BSIO
UART_CLK BILD_CLK
PERIPHERAL CONTROL LOGIC
REAL TIME CLOCK
RTC_CLK UART_CLK NPOR_RESET
UIM BUS
RTC_XIN
PLL SYSTEM CLOCK GENERATOR
PLLAT1 PR_XIN PR_XOUT CLK_I CLK_T
U2RXD U2TXD
UART2
NRESET
NRESET
BILD BUS
M_CLK
FIREFLY MF1 CORE
PER_INT MEAS_INT
UIM BUS
12-CHANNEL GPS CORRELATOR
RAW TIMEMARK M_CLK
SAMPCLK MAG0 SIGN0
DMAC U1RXD U1TXD INTC UART1 TIC SSM
SSM BDIAG/XPIN IO
TIC
ACCUM_INT
RF_PLL_LOCK IEXTINT2
NPOR_ RESET
1PPS TIMEMARK GENERATOR
TIMEMARK/TIC
ARM7 TDMI MICRO JTAG
UIM MPC
UIM BUS
SDATA[15:0]
NICE NTRST
JTAG INTERFACE
SADD[19:0]
BOOT ROM 512316
SRAM 2K332 (6ns)
JTAG
GP4020
SADD[19:0] SDATA[15:0] NSUB NSWE[1:0] NCSC[2:0] TMS TDI SWAIT NOSE TDO TCK
Figure 1 - Block diagram
2
GP4020
76
50
100 1 25
QPA100 Figure 2 - Pin connections (top view) Associated circuit block MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Signal Name SADD[0] SADD[1] SADD[2] SADD[3] SADD[4] SADD[5] GNDPWR SADD[6] SADD[7] VDD PWR NSCS[0] NSCS[1] NSCS[2A] SADD[19] SDATA[0] SDATA[1] SDATA[2] SDATA[3] GNDPWR SDATA[4] SDATA[5] VDD PWR SDATA[6]
Type I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O I/O I/O I/O
Description System Address bit 0 System Address bit 1 System Address bit 2 System Address bit 3 System Address bit 4 System Address bit 5 System Address bit 6 System Address bit 7 System Chip Select 0 - Active Low System Chip Select 1 - Active Low System Chip Select 2A - Active Low System Address bit 19 System Data bit 01 System Data bit 11 System Data bit 21 System Data bit 31 System Data bit 41 System Data bit 51 System Data bit 61
Notes
1 1 1
Cont... Table 1 - Pin descriptions All VDD and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either high or low; no inputs should be left unconnected.
3
GP4020
Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name SDATA[7] NSOE NSWE[1] NSWE[0] SDATA[8] SDATA[9] VDD SDATA[10] SDATA[11] GND SDATA[12] SDATA[13] SDATA[14] SDATA[15] SADD[18] SADD[17] SADD[16] GND SADD[15] SADD[14] VDD SADD[13] SADD[12] SADD[11] SADD[10] SADD[9] SADD[8] SWAIT Type I/O I/O I/O I/O I/O I/O PWR I/O I/O PWR I/O I/O I/O I/O I/O I/O I/O PWR I/O I/O PWR I/O I/O I/O I/O I/O I/O I Associated circuit block MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC MPC Description System Data bit 7 System Output Enable, active low System Write Enable bit 1, active low System Write Enable bit 0, active low System Data bit 8 System Data bit 9 System Data bit 10 System Data bit 11 System Data bit 12 System Data bit 13 System Data bit 14 System Data bit 15 System Address bit 18 System Address bit 17 System Address bit 16 System Address bit 15 System Address bit 14 System Address bit 13 System Address bit 12 System Address bit 11 System Address bit 10 System Address bit 9 System Address bit 8 System Wait input - allows wait-states to be inserted into the current Firefly clock cycle. System Upper Byte, active low. Interrupt source 2 input (for external interrupts). Multi-function Input / Output. Used to set Boot Up ROM area, and source either 100kHz square wave or System Clock. Discrete Input / Output. Used either as input or to source RF_Power_Down control signal or TIC. PLL Lock Indicator input from RF section. When high this signal indicates that the PLL within the RF section is in lock and the master-clock inputs have stabilised. VDD Supply for CLK_T & CLK_I input block in the System Clock Generator. This pin should be well decoupled to pin 60 (GND) to ensure optimum noise immunity Master Clock Input from RF front end 40MHz 100mV rms. Inverted Master Clock Input from RF front end: 40MHz 100mV rms. Notes 1 1 1 1 1 1 1 1 1 1 1 1
52 53 54
NSUB IEXTINT2 MULTI_FNIO
O I I/O
MPC INTC PCL
1,2
55
DISCIO
I/O
PCL
3
56
RF_PLL_LOCK
I
INTC /PCL
57
A1VDD
PWR
SCG
58 59
CLK_T CLK_I
I I
SCG SCG
4 4
Cont...
Table 1 - Pin descriptions (continued)
4
GP4020
Pin No. 60 61 62 63 64 65 66 67 Signal name GND SIGN0 MAG0 SAMPCLK POWER_GOOD PR_XOUT PR_XIN TEST Type PWR I I O I O I I Associated circuit block Description Notes
CORR CORR CORR PCL SCG SCG
Sampled Sign (polarity) data from RF front end. Sampled Mag (amplitude) data from RF front end. Sample Clock output to the RF front end. Provides a 5*714MHz clock with a 4:3 mark to space ratio. Power Monitor input, high for normal operation; low forces the GP4020 into Power Down mode. System Clock Oscillator - crystal output for 10 to 16MHz crystal. System Clock Oscillator - crystal inputfor 10 to 16MHz crystal. TEST select pin,used with TESTMODE (pin 74). Used for test purposes only and should be connected to GND in normal operation. Timemark output. This pin can be used to produce a UTC-aligned 1 PPS output, or TIC output. TEST select pin,used with TESTMODE (pin 74). Used for test purposes only and should be connected to GND in normal operation. Real-time Clock Oscillator input for 32kHz crystal. Real-time Clock Oscillator output for 32kHz crystal. TEST select pin,used with TEST (pin 67). Used for test purposes only and should be connected to GND in normal operation. System Reset input. UART 2 Transmit data output. UART 2 Receive data input. UART 1 Transmit data output. UART 1 Receive data input. GND connection for PLL Block. VDD connection for PLL Block.
5
68 69 70
VDD TIMEMARK / TIC IDDQTEST
PWR O I
1PPS
71 72 73 74
GND RTC_XIN RTC_XOUT TESTMODE
PWR I O I
RTC RTC
5
75 76 77 78 79 80 81 82 83
NSRESET U2TXD U2RXD U1TXD U1RXD PLLGND PLLVDD GND PLLAT1
I O I O I PWR PWR PWR O
PCL UART2 UART2 UART1 UART1 SCGPLL SCGPLL SCGPLL
3 3
84 85 86
NICE VDD TCK/bdiag[0]/XReq
I PWR I/O
JTAG/SSM MUTIPLEX JTAG/SSM
System Clock Generator PLL Analog Test I/O. Reserved for TEST purposes only and should NOT be connected in normal operation. ARM7 operating mode and JTAG / SSM Signal Multiplex (pins 86, 87, 88, 89).
JTAG Test Clock/SSM Diagnostic broadcast debug output bdiag[0]/System test control input XReq. JTAG Test Data In/SSM Diagnostic broadcast debug output bdiag[1]/System Test control input X/Write. JTAG Test Data Out/SSM Diagnostic broadcast debug output bdiag[2]/System test control input XBurst.
6
6
87
TDI/bdiag[1]/XWrite
I/O
JTAG/SSM
6
88
TDO/bdiag[2]/XBurst
I/O
JTAG/SSM
6
Table 1 - Pin descriptions (continued)
Cont...
5
GP4020
Pin No. 89 Signal name TMS/bdiag[3]/XCon Type I/O Associated circuit block JTAG/SSM Description JTAG Test Mode Select/SSM Diagnostic broadcast debug output bdiag[3]/System test control input XCon. JTAG interface Reset or SSM debug interface multiplex (pins 86, 87, 88 and 89). General Purpose Input/Output 7. Can be multiplexed to SCG PLL Digital Test Output (PLLDT1). General Purpose Input/Output 6. General Purpose Input/Output 5. Can be multiplexed to DISCOP discrete output from correlator. General Purpose Input/Output 4. Also directly connects to DISCIP1 on the 12-channel correlator. General Purpose Input/Output 3. Can be multiplexed to BSIO Slave Select[1]. General Purpose Input/Output 2. Can be multiplexed to BSIO Slave Select[0]. General Purpose Input/Output 1. Can be multiplexed to BSIO Data Input/Output. General Purpose Input/Output pin 0. Can be multiplexed to BSIO_CLK output. Notes 6
90 91
NTRST GPI0[7]/PLLDT1
I I/O
JTAG/SSM GPIO/SCG PLL
6 3
92 93
GPIO[6] GPIO[5]/DISCOP
I/O I/O
GPIO GPIO/CORR
3 3
94 95 96 97 98 99 100
GND GPIO[4]/DISCIP1 GPIO[3]/BSIO_SS[1] GPIO[2]/BSIO_SS[0] VDD GPIO[1]/BSIO_DATA GPIO[0]/BSIO_CLK
PWR I/O I/O I/O PWR I/O I/O
GPIO/CORR GPIO/BSIO GPIO/BSIO
3 3 3
GPIO/BSIO GPIO/BSIO
3 3
Table 1 - Pin descriptions (continued) NOTES 1. High impedance is achieved on pins 11 to 18, 20, 21, 23 to 29, 31, 32, 34 to 37 when either: (a) Data is not being written from GP4020. (b) POWER_GOOD (pin 64) is low. (c) Bit 1 (RF_PD) of POW_CNTL register is high. (d) Bit 10 (RF_SLEEP) of POW_CNTL register is high. 2. NSUB (pin 52) is the Upper Byte select output from the Memory Peripheral Controller, when single chip 16-bit memories with NUB and NLB inputs are used. NSUB maps to NUB and address line SADD[0] to NLB. 3. Input is tolerant to being driven with a +5V HIGH level, as well as +3*3V HIGH nominal level. 4. Both CLK_T (pin 58) and CLK_I (pin 59) should not have an external DC bias of GREATER than +1*7V . Direct connection from a GP2010/GP2015 RF front end is NOT possible, without bias-shift circuit (Figure 3). 5. TEST (pin 67) and TESTMODE (pin 74) are used together to set up manufacturing test modes for the GP4020, as shown in Table 2 (0 = GND, 1 = VDD). TEST (pin 67) 0 1 0 1 TESTMODE (pin 74) 0 0 1 1 Test function Normal operation Firefly Macrocell test mode Firefly System test mode UIM logic test mode
Table 2 - Test mode truth table Details of ALL test modes are covered in section 2.10 of the Zarlink Semiconductor Firefly MF1 Core Design Manual.
6
GP4020
NOTES (continued): 6. NICE (pin 84) and NRST (pin 90) control a number of operation modes and a debug on signal multiplex on pins 86 to 90 as follows: NICE = low ARM7TDMI in ICE mode. ARM7TDMI will not access memory unless instructed by the JTAG interface. NTRST (pin 90) set Low will reset the JTAG. NICE = High ARM7TDMI in Normal mode. ARM7TDMI does not effect the reset on the JTAG inteface. However, a reset of Firefly will also reset the JTAG. NTRST (pin 90) has a reset and signal-multiplex function, dependent on the state of NICE (pin 84): (i) NICE = Low: JTAG debug signals connected to pins 86, 87, 88, 89 & 90, as follows: Pin 86 = TCK = JTAG clock in Pin 87 = TDI = JTAG data in Pin 88 = TDO = JTAG data out Pin 89 = TMS = JTAG mode select in Pin 90 = NTRST = Active low reset to JTAG interface (JTAG interface also reset when Firefly MF1 is reset) (ii) NICE = High and NTRST = High: Normal mode of operation for GP4020. System Services Module Broadcast Diagnostic debug output signals connected to pins 86, 87, 88, 89 as follows: Pin 86 = bdiag[0] Pin 87 = bdiag[1] Pin 88 = bdiag[2] Pin 89 = bdiag[3] Diagnostic mode must have been set-up using the Diagnostic Configuration Registers within Firefly MF1. Refer to Section 8 of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more information. (iii) NICE = High & NTRST = Low: Firefly MF1 System Test Control input signals connected to pins 86, 87, 88, 89 as follows: Pin 86 = Xreq Pin 87 = XWrite Pin 88 = Xburst Pin 89 = XCon System test inputs are used in Firefly MF1 macrocell test mode for manufacturing test. Refer to Section 2.10 of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more information.
Glossary:
1PPS ARM(R) ARM7TDMITM 1 Pulse Per Second Advanced RISC Machines ARM7 microprocessor with Thumb, Debug, fast Multiplier and ICE Breaker Extensions Bus for Controller Integration in LowPower Designs BILD bus system clock BILD Serial Input / Output 12-channel Correlator Direct Memory Access Controller Zarlink Semiconductor microcontroller cell, based on ARM7TDMI, DMAC, INTC, MPC, SYSTIC and UART General Purpose Input / Output Global Positioning System ICE INTC MPC PCL PLL RAM ROM RTC SCG SSM SYSTIC TIC UART UIM WDOG In Circuit Emulation Interrupt Controller Memory Peripheral Controller Peripheral Control Logic Phase Locked Loop Random Access Memory Read Only Memory Real Time Clock System Clock Generator System Services Module System Timer / Counter module Timer / Counter Universal Asynchronous Receiver/ Transmitter Up-Integration Module Watchdog
BILD B_CLK BSIO CORR DMAC Firefly MF1
GPIO GPS
7
72 84
73
JTAG INTERFACE
8
10p 10p 32kHz CRYSTAL 10M 22k STATIC RAM (16-BIT) 13*3V
GP4020
ANTENNA
1575MHz RF FILTER 10MHz TCXO
RTC_ XIN RTC_ XOUT
SYSTEM SERVICES ICE ARMTDMI
NICE
13*3V 1M 1M
58 17
REAL TIME CLOCK TIMER/ COUNTER (32)
CLK_T BILD_ CLK
OPCLK1
16 59
10n
FIREFLY MF1 MICROCONTROLLER
DMA CONTROLLER MEMORY PERIPHERAL CONTROLLER
FLASH EPROM (16-BIT)
175MHz LC FILTER
OPCLK2 CLK_I
10n 1M 1M
INTERRUPT CONTROLLER
75
SYSTEM CLOCK GENERATOR WITH PLL
13*3V 22k
NSRESET M_CLK LD
9 64 21 56
13*3V
UART 1
SERIAL COMMS PORT 1
GP2015
RF_PLL_LOCK
3*3k 1*5V
RESET LOGIC
8
GP4020
UART 2
SERIAL COMMS PORT 2
PREF
10n
POWER_GOOD
2*7k
PRESET
WATCHDOG
SIGN SIGN0 MAG0 MAG
11 14 62
15
470
61
35MHz SAW FILTER
470 1k
63
12-CHANNEL CORRELATOR
BSIO 3-WIRE SERIAL INTERFACE
GENERAL PURPOSE I/O (8 LINES)
GPIO / BSIO
Figure 3 - Block diagram of a typical GP4020-based GPS receiver
CLK SAMPCLK RAW_TIMEMARK
67 70
TEST IDDQTEST
BOOT ROM
SRAM (2K332)
1 PPS GENERATOR
69
1 PULSE PER SECOND
GP4020
Typical GPS Receiver
Figure 3 shows a typical GPS receiver employing a GP2015 RF front end and a GP4020 correlator. The RF section, GP2015, performs down conversion of the L1 (1575*42MHz) signal for digital baseband processing. The resultant signal is then correlated in the GPS correlator within the GP4020 with an internally generated replica of the satellite PRN code to be received. Individual codes for each channel may be selected independently to enable acquisition and tracking of up to 12 different satellites simultaneously. The results of the correlations form the accumulated data and are transferred to the microprocessor to give the broadcast satellite data (the Navigation Message) and to control the software signal tracking. The ARM7TDMI is object code compatible with all earlier ARM6 and ARM7 based products. The ARM7TDMI is a fully static design and as such consumes dynamic power only when clocked.
Boot ROM
The GP4020 BOOT ROM contains code which is executed every time there is a complete system reset (i.e. when main power has been removed from the GP4020). The code installed on the BOOT ROM, allows the GP4020 to undertake either of 2 functions after a complete reset: * Run External Flash EPROM from the EPROM base address. * Load into the internal SRAM a unique program via the UART1 input. This could be used for test purposes, although the target use of this facility is to allow for field upgrades of GPS receiver firmware, in conjunction with a Flash EPROM.
Device Description
The GP4020 is a complete baseband processor for Navstar GPS C/A code signals. It incorporates a 12channel GPS correlator, a Zarlink Firefly MF1 microcontroller core (incorporating the ARM7TDMI Thumb microprocessor), Real Time Clock, 8KBytes of on-chip SRAM and a boot ROM. The GP4020 uses a fully configurable memory interface, allowing the use of 16-bit external memory. A block diagram of the GP4020 is shown in Figure 1. The GP4020 GPS Baseband processor features: * Firefly MF1 Core including ARM7TDMI Microprocessor * 12-channel Navstar GPS C/A code correlator * 1KByte Onboard Boot ROM * 8KByte Onboard SRAM * 8-bit General Purpose I/O * Debugging Serial Access Ports - JTAG or SSM * System Timer / Counters * Real Time Clock * BSIO: 3-wire serial interface * Watchdog * 1Pulse-Per-Second output, with 25ns resolution * Flexible system Clock Generator - can use clock source from a crystal or from RF front end TCXO
BILD Bus
This is a modular bus architecture and specification, via which all on-chip modules communicate with each other. These modules can either be bus masters or slaves. A bus master can initiate a bus access, generate addresses and control read or write transfers. A bus slave responds to a bus master request when selected by the system address decoder, and may, if required, assert a wait signal on the bus until the relevant data transfer has been completed. All internal data transfers on the module bus are single cycle. The Firefly MF1 micro-controller has three modules that are capable of operating as Bus masters. These are the ARM7TDMI Core, DMAC and SSM, described below.
BILD Serial Input Output (BSIO)
This module produces a 2-channel 3-wire serial interface for up to 2 external `Slave' serial interface devices (e.g. serial EEPROM). It provides both Micro-wire Interface and Serial Peripheral Interface (SPI) compatibility.
ARM Processor (ARM7TDMI)
The ARM7TDMI is a 32-bit RISC microprocessor core designed by Advanced RISC Machines (ARM). It uses a series 7 microprocessor core, with the following functional extensions: * * * * Thumb (16-bit) instruction set Debug interface using J-TAG Fast Multiplier Embedded In-Circuit Emulation capability
12-Channel Correlator
This module contains 12 channels of PRN code correlators for spread-spectrum correlation of 12 simultaneous signals. Each channel contains an independent carrier DCO to allow independent mix down of a satellite signal to baseband before code correlation occurs. The correlator is designed to extract data modulated at a nominal chipping rate of 1*023Mbps, and can be used on both Navstar C/A code GPS signals and Inmarsat WAAS codes.
9
GP4020
DMA Controller (DMAC)
Two DMA engines are available on the microcontroller. These are configured as a pair to provide a memory-tomemory DMA capability between any 2 locations in the ARM7TDMI memory space. They may be used independently for high speed fly-by transfers between UART1 (or UART2) and either on-chip or off-chip locations. Single or multiple byte transfers (Demand or Burst Mode) are supported and may be word, half word or byte wide.
General Purpose Input Output (GPIO)
This module provides 8 I/O pins, which may be bit or byte addressed and configured in a latched or transparent mode. External Interrupts can be set for edge or level sensitivity with a polarity option. To minimise interrupt latency, there is a hard-wired priority scheme for each channel for both FIQ and IRQ; alternatively this can be ignored and the priority assessment handled in software.
Memory/Peripheral Controller (MPC)
The MPC ensures the correct multiplexing of data is applied for bus transfers between 8, 16 or 32-bit on-chip or off-chip peripherals. Four different contiguous memory areas are available, each with an address range of 1 MByte, with individually programmable wait and stop state generation. A SWAP function allows memory area 1, which is addressed at system reset, to be switched with memory area 4. This allows, for example, booting from ROM and then switching memory area 1 to address SRAM so that time-critical software and interrupt routines can operate from fast memory.
Embedded Microcontroller Debug Options
The Firefly MF1 Core incorporates three sophisticated methods of hardware and software debug. The options are:
q q q
Embedded ICE, accessed via the ARM7TDMI JTAG interface (Multi ICE access also possible) Angel Debug Monitor Logic Analyser coupled with an Inverse Assembler, accessed via the SSM debug interface
The GP4020 can use any of these options, but special emphasis has been placed on the Embedded ICE and Logic Analyser options. The JTAG and SSM debug interfaces are multiplexed onto the same pins, and can be selected by setting NICE (pin 84) high for SSM, or low for JTAG.
Peripheral Control Logic (PCL)
The GP4020 incorporates some specific control logic, which is used to control a number of functions: * * * * System Reset Control System Power-down, Sleep and Wake-up Control System Status and Control Registers Signal input/output multiplex control
Firefly MF1 Microcontroller core
The Firefly MF1 Microcontroller is an Embedded Microcontroller core developed by Zarlink Semiconductor. It combines the processing power of the ARM7TDMI microprocessor with a number of peripheral components: * Direct Memory Access Controller (DMAC) * Interrupt Controller (INTC) * Memory Peripheral Controller (MPC), incorporating Up-Integration Module (UIM) * System Services Module (SSM) * System Timer/Counter (SYSTIC) * Universal Asynchronous Receiver / Transmitter (UART)
RAM
The GP4020 contains 8KBytes (configured as 2K332-bit) of high-speed (6ns) Static RAM. This can be used for either: * Non-volatile storage of GPS data (Almanac, Ephemeris, Position and Receiver Clock Offset), while the receiver power is disabled * A High-speed Interrupt Service Routine, while the GP4020 is powered up The internal SRAM appears at GP4020 Base Address 0x60000000, served by the MPC Memory Area 4. An MPC SWAP function can swap this memory space with 0x00000000 if required.
Interrupt Controller (INTC)
The ARM7TDMI core accepts two types of interrupt: Normal (IRQ) and Fast (FIQ). All Interrupts can be switched between types, depending upon the relative priorities required. The INTC is the central control logic that decodes the priority level and handles interrupt request signals from a total of 8 fixed pre-defined, internal sources and a number of external sources.
10
GP4020
Since the memory is high-speed, it can be accessed with Zero wait-states through the Memory Peripheral Controller. Refer to section on the Memory Peripheral Controller for more information. * Interface to external bus masters and manufacturing testers * Control the activities of all BILD bus modules during system debug activity. * Broadcast information about BILD bus activity for external diagnostics * Hold BILD bus logic levels when no other busmaster is driving * Register System Configuration data
Real Time Clock (RTC)
The GP4020 Real Time Clock uses an external 32kHz crystal to give an indication of time to the GP4020 chip, when the device is in Reset / Power Down. If a backup battery is included in a GPS receiver using the GP4020, the RTC will continue to operate regardless of the reset state of the rest of the device. The RTC is incremental, which means that the number of seconds from a reset point are accumulated, rather than a record of Gregorian date.
System Timer/Counters (SYSTIC)
Two dual independent 32-bit timer/counters, with an 8bit pre-scaler capability for each counter, are provided (Timers 1A, 1B, 2A and 2B). These are synchronous to the system clock and may be polled, or set-up to generate interrupts on over-run, with auto-reload. The TIC functions provided by this module are part of the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020 Base Address 0xE000 E000, and Timer 2 (TIC2) appears at Address 0xE000 F000. TIC enable (TEN) lines are not available externally on this version of the GP4020, but are tied low on-chip. The TIC functions can be made available by setting the External enable polarity bit of the TIC Control/Status register to a logic `0'. Whilst these timer/counters are NOT required by the GPS function in a GP4020 based GPS receiver, full programming details of the programming of the System Timer/Counter can be found in Section 7 of the Firefly MF1 Core Design Manual.
System Clock Generator (SCG)
The GP4020 System Clock Generator is used to provide 2 system clocks: * The M_CLK for the 12-channel Correlator; this is derived from the CLK_T and CLK_I inputs from the RF front end device and MUST be 40MHz. This clock is fundamental to the correlator function, and must be phase-locked to the RF front end.
* The BILD_CLK for ALL components on the BILD
Bus; this can be derived from M_CLK (see above) in conjunction with a PLL and a divider to generate a wide range of clock frequencies. In this way, the BILD_CLK can be phase-locked to the RF front end. The clock can also be derived from an independent crystal source.
1PPS Timemark Generator
The GP4020 Timemark generator is used in conjunction with software to produce a 1 Pulse Per Second (1PPS) output pulse, which is aligned to Universal Time Co-ordinated (UTC) to a resolution of 25ns. The accuracy of time transmitted from the Navstar GPS space segment is very high, and this can be used to provide a mobile timing reference to a similar accuracy.
System Services Module (SSM)
The System Services Module (SSM) ensures correct bus operation through a number of modes (reset, initialisation, debug, etc). It provides diagnostic broadcast of address and data for internal transfers along with information about the current operating mode. Additionally the SSM System Configuration Register controls the operating mode of the GP4020. Specifically the System Services Module performs the following functions: * Control the BILD bus operational mode * Arbitrate amongst competing resources for BILD bus mastership
Up Integration Module (UIM)
The Up Integration Module provides a series of internal connection ports, which mimic the MPC external interface. This allows the Firefly MF1 to communicate with the Application Specific Logic used in the GP4020, as though it was external to the chip, hence it acts as a transparent interface.
11
GP4020
Universal Asynchronous Receive/Transmit (UART1 and UART2)
The full duplex asynchronous channels of UART1 and UART2 provide RS232 type interfaces, which support an XON/XOFF software protocol. The Receive and Transmit channels are double buffered. The UARTs may be polled, or may use an interrupt scheme for module bus transfers. An internal Baud rate generator in each UART can provide selectable data rates, derived from on-chip sources for an Rx/Tx pair. Directly-triggered DMA transfers with each UART are also possible without the need for CPU intervention.
Watchdog (WDOG)
The GP4020 Watchdog can be used to detect hardware or software run-time errors, and reset the system. The processor is required to reset the watchdog periodically; failure to do so will result in a chip-wide reset.
Electrical Characteristics
TAMB = -40C to +85C, VDD = +3*0V to +3*6V (+3*3V nominal). The input thresholds and output voltage limits for the logic signal pins are tested and guaranteed by production test. All other parameters are guaranteed by characterisation and design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise specified. Use in conjunction with the GP4020 GPS Baseband Processor Design Manual (DM5280). Characteristic Operating voltage range Battery backup voltage Supply Current Full chip Symbol Min. 3*0 2*7 Value Typ. Max. 3*6 Units V V mA Simulated. Firefly BlLD_CLK = 30MHz, outputs loaded with 50pF, 12 tracking correlator channels Enabled Disabled Enabled Disabled Disabled Enabled - FOUT = 30MHz, Mult Factor = 3 Enabled - FOUT = 60MHz, Mult Factor = 6 Enabled - FOUT = 1 20MHz, Mult Factor = 12 Enabled - FOUT = 240MHz, Mult Factor = 24 Conditions
VBATT IDD
100
40MHz low level differential input ILLDI Processor clock oscillator Phase locked loop IPRX <100 IPLL 2*9 3*4 4*5 6*2 Real time clock Firefly MF1 microcontroller Firefly MF1 microcontroller Operating frequency IRTC IFMF1 FBILD 3*27 0*7 20
4*4 100 0*9 1*0
mA nA mA nA A mA mA mA mA
7*75
A mA/MHz MHz
31*25
Operating frequency Output capacitance
FBILD
20
27.5 50
MHz pF
Bild_CLK - external memory at >1 wait state or internal memory at 0 wait state. Bild_CLK - external memory access at 0 wait state. Total external load, all outputs and I/Os
Cont...
12
GP4020
Electrical Characteristics (continued)
Characteristic 40MHz Low Level Differential Input Input voltage bias Differential input voltage Input differential hysteresis Input clock frequency Input capacitance Power-on delay Processor Clock Oscillator Frequency Start up time Mark:space Transconductance Output impedance Feedback resistance Phase Locked Loop Input frequency Output frequency Duty cycle Phase alignment offset (falling edges of CLKINB, CLKFBKB) Phase Alignment Jitter Phase Jitter CLKINB to CLKOUTB delay PLL Settling Time Real Time Clock Crystal frequency Start up time Transconductance Output impedance Feedback resistance BILD Serial Input / Output (BSIO) 3-wire Bus Interface BSIO_CLK output frequency Serial clock output low period Serial clock output high period Serial clock output rise time Serial clock output fall time Serial data output delay Serial enable output delay Serial chip select enable to first clock edge delay Serial last clock edge delay to chip select disable Symbol Min. 0 100 12 40 5 Value Typ. Max. 1*715 24 150 150 FPRXIN TPRXSU gm ZO RF FPLLIN FPLLOUT 10 45 1*0 10 50 2*24 93 220 16 55 4*4 Units Conditions
VDBIAS VDIFIN VDIFHYS FDIFIN CDIFIN
V mV mV MHz pF ns MHz ms % mA/V k k MHz MHz % ns ns ns ns s kHz ms A/V M M
Min. VDD = 3*0V Note 1
40MHz from RF front end Not including package
Correct external components Across frequency range Across all conditions
10 10 45 50
20 250 55 +-0*2 +-0*25 +-0*15
Can be divided down by 1,2,4 or 8 for optimal BlLD_CLK freq.
TPLLSET FRTC TRTCSTART GMRTC ZORTC RFRTC
0*43 147 32*768 400 9*56 422 10
Note 2 Cycle-cycle edge jitter Note 2 In clock bypass mode In clock synchronisation mode Correct external components Across frequency range
External component
FSEROF TSERCL TSERCH TSERCR TSERCF TSERDOD TSEREOD TSERCDC TSERCEC
10 40 40 10 10 20 20
-2 0 -2 0 70 70
MHz ns ns ns ns ns ns ns ns
SEROUT ref SERCLK SERSEL ref SERCLK
Cont... NOTES 1. The input pair CLK_T, CLK_I may be driven by a low amplitude differential sinewave from an RF Front-end. Direct DC connection to a GP2010 or GP2015 RF front end is NOT possible, as the maximum DC bias from these devices is in excess of maximum input bias limit. 2. Jitter is dominated by supply-noise effects. Users must keep on-chip supply noise below 1Vp-p by the use of low noise outputs and as many supply pins as possible.
13
GP4020
Electrical Characteristics (continued)
Characteristic General Purpose Input/Output (GPIO) Output delay Input set-up time Input hold time UARTs Standard Baud rate Reset logic Input reset pulse width Symbol Min. Value Typ. Max. 20 20 10 1*2 100 115*2 Units Conditions
TGPOD TGPIS TGPIH BDPUS
ns ns ns kBaud ns
GPIO[7:0] GPIO[7:0] GPIO[7:0] U1/2TXD, U1/2RXD NSRESET input to cause reset of whole chip
14
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